Part 7 - Timing, delay & power

When designing digital circuits, the timing, delay and power usage of the circuit are important. In this part we’ll cover how we usually measure and compare these.

Timing and delay

In an arbitrary synchronous circuit, we usually have:

• A single-bit clock, all other wires may be multiple bits wide.
• Registers (Which is just a collection of flip-flops).
• The clock will be distributed to all flip-flops
• Combinational logic
  • No internal state
  • Output only a function of input(s)
• Particular inputs/outputs are optional
• Optional feedback(-loops).

So how do we measure the performance/how fast a circuit is? We could do, operations/sec, or cycles/sec? But we need to know what limits the clock rate and what happens if we increase the clock rate.

If we break this down, what causes delay?

• Logic gate delay
• (Physical) Wire delay
• Delays in flip-flops

Only one of these delays can cause a faulty cycle. Since flip-flops require a setup time and a clock to Q delay. We can have situations where, if the clock is too fast, the flip-flops output the wrong things.

When analyzing circuits, we only care about the critical path - if the clock is too fast for this path, the whole circuit falls.

There are 4 general cases:

• Input $\to$ CL $\to$ Output
• Input $\to$ CL $\to$ Register
• Register $\to$ CL $\to$ Output
• Register $\to$ CL $\to$ Register

Therefore, in general the clock period, $T$, should be:

T = time(input setup) + time(CL) + time(wire) + time(output setup)

Gate delay

The time needed for the output of a gate to change from the moment an input of the gate changes depends on:

• Transistor parameters
• Fan-out: how many wires it will drive
• Fan-in: number of inputs of a gate

Wire Delay

In general, wires behave as the transmission lines, signal wave-front moves close to the speed of light.

Wire delay is also proportional to the square of its length, $\mathcal{O}(L²)$

Flip-flop delay

As we earlier covered, flip-flops have a certain delay.

These are:

• Setup time
  • The time the input of a flip-flop needs to be stable, before the clock edge to be stored correctly
• Hold time
  • The time the input of a flip-flop needs to be held, after the clock edge to be stored correctly
• Propagation time
  • The time a flip-flop needs to propagate a value stored to the output

Metastability

Asynchronous inputs can be really dangerous, therefore synchronous inputs are preferred.

The solution to this is having a so-called synchronizer blocks (usually two registers).

A synchronizer design is characterised by its Mean Time Between Failure (MTBF).

There is a nice equation: $$ MTBF(t_r) = \frac{e^{\frac{t_r}{\tau}}}{T_0 \cdot\ f \cdot\ a} $$

Where: $$ t_r = \text{resolution time (clock period - FF setup time)} \newline T_0, \tau = \text{flip-flop characteristic constants} \newline f = \text{clock frequency} \newline a = \text{average input rate of change} $$

Power

Time for a bit of math and physics:)

The power supply provides energy for charging and discharging wires and transistor gates. The energy is stored and dissipated as heat.

Let’s remember that: $$ P = \frac{dE}{dt} $$

And that, voltage (potential of the charge) is increased the amount of energy, $dE$, needed to move an amount of charge, $dq$.

$$ V = \frac{dE}{dq} $$

And current is: $$ I = \frac{dq}{dt} $$

Then: $$ \frac{dE}{dt} = \frac{dE}{dq} \cdot\ \frac{dq}{dt} = \boxed{P = V \cdot\ I} $$

Which means: $$ E = \int_{-\infty}^t\ P\ dt $$

Remember that power and energy is not the same in the physics world, even if we may use them interchangeably in every-day terms.

Metrics

These are some of the metrics that we usually study in digital circuits

Average power: $$ P_{avg} = \frac{\Delta E}{\Delta t} $$

Peak power: $$ P_{peak} = \max\left(\lim_{\Delta t \rightarrow 0}\ \frac{\Delta E}{\Delta T}\right) = \max\left(\frac{dE}{dt}\right) $$

One of the most popular metrics is performance per watt (measures energy efficiency).